EP3C16F484C6, which is the FPGA chip on the Altera DE0 board. To learn about the format of a memory initialization file (MIF), see the Quartus II Help. A MIF is used as an input file for memory initialization in the Compiler and Simulator. You can also use a Hexadecimal (Intel-Format) File (.hex) to provide memory initialization data. A MIF contains the initial values for each address in the memory. A separate file is required for each memory block. In a MIF, you are also required to specify the memory depth and width values.
$begingroup$I was running PCI Express reference design simulation in Modelsim. Compilation failed and an error 'cannot open top_core.vo file in read mode' was displayed. I went through respective folder, but that particular file was missing. A verilog file with same name (top_core.v) is there is same location.
After going through all the document what I understood is, verilog output file is created by Quartus II when compiled. Then why it is not happening in my case. Is there any other method to make top_core.vo from top_core.v file ?
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$begingroup$A .vo file is a 'verilog output' file. It should be generated in the $PROJECT/simulation/modelsim/ directory. It contains your top level verilog module plus annotations that specify the timing constraints for the IO pins of your actual device so that the simulator can verify the setup-and-hold times of the IO.
![Quartus Mif File Quartus Mif File](/uploads/1/2/3/9/123914478/685263636.png)
You can generate it from the menu Processing >> Start >> Start EDA Netlist Writer, then you can add it to your simulation.
I think you can do functional (rather than timing) simulation by simply using the original .v source file, but honestly I don't have it working yet either.
EvanEvan
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I made an entity in which quartus successfully recognizes RAM, and instantiates a RAM megafunction for it. It would be nice if I could initialize that RAM from a file. I found tutorials for making such file (.mif file). Now that I have created that file, i don't know how to make quartus initialize that module. Any help is appreciated.
Here is my RAM entity:
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4 Answers
One simple way to initalize a ram area is as follows:(quartus 15.1 tested)
Best regards,Johi.
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JohiJohi
Possibly the best way to initialise the memory is to ... put an initialisation clause on the memory variable. There may be Quartus-specific ways to load .MIF files, but this is probably simpler, definitely more portable (to Xilinx for example), and more flexible because you get to define the file format, you don't have to generate .mif files.
Given the following code:
you could simply write
Now it is possible but unlikely that Quartus doesn't support initialisation this way,so we can test it by writing a simple init_my_ram function ignoring the actual file contents:
Because the function call is an initialiser, and called at elaboration time when the design is synthesised, this is all synthesisable.
If this compiles and Quartus generates a memory full of X'55', you are good to go, to parse whatever file format you want, in the init_my_ram function. (Binary files are harder, and the reader code may not be so portable between tools, but not impossible).
The .MIF approach has one potential advantage though : you can update just the memory contents without requiring another synthesis/place and route cycle.
Brian DrummondBrian Drummond![Quartus Mif File Quartus Mif File](http://www.sugawara-systems.com/tutorial/mif6.png)
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If you generated one of the RAM modules using the wizard but forgot to add a memory initialization file to it you can add one later by doing the following:
Tools > MegaWizard Plug-In Manager > Edit an existing custom megafunction variation > {Select your file} > Next > Mem Init > Yes, use this file for the memory content data > Browse
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As specified in this document this is the proper way to init memory from file:
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